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3–18
Chapter 3: Design Rules and Procedures
Timing Semantics Between Simulink and HDL Simulation
If you turn on the optional ports in the Block Parameters dialog box for each of the
DSP Builder registered blocks, you can access and drive the clock enable and reset
input pins graphically in the Simulink software.
In the HDL domain, the registered DSP Builder blocks uses an asynchronous reset, as
this behavioral VHDL code example shows:
process(CLOCK, RESET)
begin
if RESET = '1' then
dout <= (others => '0');
else if CLOCK'event and CLOCK = '1' then
dout <= din;
end if;
end
In addition, when targeting a development board, the Block Parameters dialog box
for the DSP Board configuration block typically includes a Global Reset Pin selection
box where you can choose from a list of pins that correspond to the DIP and
push-button switches.
The reset logic polarity can be either active-high or active-low. When you select
active-low, the value of the reset signal in Simulink simulation is still 0 for inactive
and 1 for active. However, DSP Builder inserts a NOT gate on the input pin in the
generated hardware. The value of the reset signal in simulation is therefore the value
as it exists across the internal design, rather then the value at the input pin.
Quartus ? II synthesis interprets this reset as an asynchronous reset, and uses an input
of the logic element look-up table to instantiate the function. The HDL simulates
correctly in this case because the testbench produces the reset input as required.
Reference Timing Diagram
Figure 3–17 shows the timing relationships in a hypothetical case where a register is
fed by the output of a counter. The counter output begins at 10—the value is 10 during
the first Simulink clock step.
Figure 3–17. Single-Clock Timing Relationships
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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